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PD - 91693A
IRL3402S
HEXFET(R) Power MOSFET
l l l l l
Advanced Process Technology Surface Mount Optimized for 4.5V-7.0V Gate Drive Ideal for CPU Core DC-DC Converters Fast Switching
D
VDSS = 20V RDS(on) = 0.01
G S
Description
ID = 85A
These HEXFET Power MOSFETs were designed specifically to meet the demands of CPU core DC-DC converters in the PC environment. Advanced processing techniques combined with an optimized gate oxide design results in a die sized specifically to offer maximum efficiency at minimum cost. The D2Pak is a surface mount power package capable of accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible onresistance in any existing surface mount package. The D2Pak is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0W in a typical surface mount application.
D 2 Pak
Absolute Maximum Ratings
Parameter
ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C V GS VGSM EAS IAR EAR dv/dt TJ TSTG Continuous Drain Current, VGS @ 4.5V Continuous Drain Current, VGS @ 4.5V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Gate-to-Source Voltage (Start Up Transient, tp = 100s) Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds
Max.
85 54 340 110 0.91 10 14 290 51 11 5.0 -55 to + 150 300 (1.6mm from case )
Units
A W W/C V V mJ A mJ V/ns C
Thermal Resistance
Parameter
RJC RJA Junction-to-Case Junction-to-Ambient ( PCB Mounted,steady-state)**
Typ.

Max.
1.1 40
Units
C/W 03/03/04
IRL3402S
Electrical Characteristics @ TJ = 25C (unless otherwise specified)
Parameter Drain-to-Source Breakdown Voltage V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient V(BR)DSS RDS(on) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LS Ciss Coss Crss Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Min. 20 0.70 65 Max. Units Conditions V VGS = 0V, ID = 250A V/C Reference to 25C, ID = 1mA 0.010 VGS = 4.5V, ID = 51A 0.008 VGS = 7.0V, ID = 51A V VDS = VGS , ID = 250A S VDS = 10V, ID = 51A 25 VDS = 20V, VGS = 0V A 250 VDS = 16V, V GS = 0V, TJ = 150C 100 VGS = 10V nA -100 VGS = -10V 78 ID = 51A 18 nC VDS = 10V 30 VGS = 4.5V, See Fig. 6 VDD = 10V ID = 51A ns RG = 5.0, VGS = 4.5V RD = 0.19, Between lead, nH 7.5 and center of die contact 3300 VGS = 0V 1400 pF VDS = 15V 510 = 1.0MHz, See Fig. 5 Typ. 0.02 10 140 80 120
Source-Drain Ratings and Characteristics
IS
I SM
V SD t rr Q rr ton Notes:
Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time
Min. Typ. Max. Units
Conditions D MOSFET symbol 85 showing the A G integral reverse 340 S p-n junction diode. 1.3 V TJ = 25C, IS = 51A, VGS = 0V 72 110 ns TJ = 25C, IF = 51A 160 240 nC di/dt = 100A/s Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Repetitive rating; pulse width limited by
max. junction temperature. Starting TJ = 25C, L = 220H RG = 25, IAS =51A. ISD 51A, di/dt 82A/s, VDD V(BR)DSS, TJ 150C
Pulse width 300s; duty cycle 2%. Uses IRL3402 data and test conditions Calculated continuous current based on maximum allowable
junction temperature; for recommended current-handling of the package refer to Design Tip # 93-4
** When mounted on FR-4 board using minimum recommended footprint. For recommended footprint and soldering techniques refer to application note #AN-994.
IRL3402S
1000
VGS 7.00V 5.00V 4.50V 3.50V 3.00V 2.70V 2.50V BOTTOM 2.25V TOP
1000
I D , Drain-to-Source Current (A)
100
I D , Drain-to-Source Current (A)
VGS 7.00V 5.00V 4.50V 3.50V 3.00V 2.70V 2.50V BOTTOM 2.25V TOP
100
2.25V
20s PULSE WIDTH TJ = 25 C
1 10 100
2.25V
20s PULSE WIDTH TJ = 150 C
1 10 100
10 0.1
10 0.1
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
2.0
RDS(on) , Drain-to-Source On Resistance (Normalized)
ID = 85A
I D , Drain-to-Source Current (A)
TJ = 25 C
1.5
100
TJ = 150 C
1.0
0.5
10 2 3 4
1 V DS = 50V 20s PULSE WIDTH
5
6
0.0 -60 -40 -20
VGS = 4.5V 10V
0 20 40 60 80 100 120 140 160
VGS , Gate-to-Source Voltage (V)
TJ , Junction Temperature ( C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance Vs. Temperature
IRL3402S
6000
5000
4000
VGS , Gate-to-Source Voltage (V)
VGS = 0V, f = 1MHz Ciss = Cgs + Cgd , Cds SHORTED Crss = Cgd Coss = Cds + Cgd
15
ID = 85 A VDS = 16V
C, Capacitance (pF)
10
Ciss
3000
2000
Coss
5
1000
Crss
1 10 100
0
0 0 20 40 60
FOR TEST CIRCUIT SEE FIGURE 13
80 100 120
VDS , Drain-to-Source Voltage (V)
QG , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
1000
10000
ISD , Reverse Drain Current (A)
TJ = 150 C TJ = 25 C
OPERATION IN THIS AREA LIMITED BY RDS(on)
ID , Drain Current (A)
100
1000 10us
10
100
100us 1ms
1
10
10ms
0.1 0.2
V GS = 0 V
0.6 1.0 1.4 1.8 2.2
1 1
TC = 25 C TJ = 150 C Single Pulse
10 100
VSD ,Source-to-Drain Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
IRL3402S
LIMITED BY PACKAGE
80
EAS , Single Pulse Avalanche Energy (mJ)
100
600
TOP
500
BOTTOM
ID 23A 32A 51A
ID , Drain Current (A)
400
60
300
40
200
20
100
0 25 50 75 100 125 150
0 25 50 75 100 125 150
TC , Case Temperature ( C)
Starting TJ , Junction Temperature ( C)
Fig 9. Maximum Drain Current Vs. Case Temperature
Fig 10. Maximum Avalanche Energy Vs. Drain Current
10
Thermal Response (Z thJC )
1 D = 0.50 0.20 0.10 0.1 0.05 0.02 0.01 SINGLE PULSE (THERMAL RESPONSE) PDM t1 t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJC + TC 0.001 0.01 0.1 1
0.01 0.00001
0.0001
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
IRL3402S
R DS (on), Drain-to-Source On Resistance ( )
R DS (on), Drain-to-Source On Resistance ( )
0.020
0.012
0.011
0.015
VGS = 4.5V
0.010
0.009
ID = 85A
0.010
0.008
VGS = 7.0V
0.007
0.005 0 50 100 150 200 250 300 350
0.006 2 3 4 5 6 7 8
I D , Drain Current (A)
VGS , Gate-to-Source Voltage (V)
Fig 12. On-Resistance Vs. Drain Current
Fig 13. On-Resistance Vs. Gate Voltage
IRL3402S
D2Pak Package Outline
10.54 (.415) 10.29 (.405) 1.40 (.055) MAX. -A2 4.69 (.185) 4.20 (.165) -B1.32 (.052) 1.22 (.048) 6.47 (.255) 6.18 (.243) 15.49 (.610) 14.73 (.580) 5.28 (.208) 4.78 (.188) 1.40 (.055) 1.14 (.045) 5.08 (.200) 1.39 (.055) 1.14 (.045) 2.79 (.110) 2.29 (.090) 2.61 (.103) 2.32 (.091) 8.89 (.350) REF. 10.16 (.400) REF.
1.78 (.070) 1.27 (.050)
1
3
3X
0.93 (.037) 3X 0.69 (.027) 0.25 (.010) M BAM
0.55 (.022) 0.46 (.018)
MINIMUM RECOMMENDED FOOTPRINT 11.43 (.450)
NOTES: 1 2 3 4 DIMENSIONS AFTER SOLDER DIP. DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. CONTROLLING DIMENSION : INCH. HEATSINK & LEAD DIMENSIONS DO NOT INCLUDE BURRS.
LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE
8.89 (.350) 17.78 (.700)
3.81 (.150) 2.08 (.082) 2X 2.54 (.100) 2X
Part Marking Information
D2Pak
INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE
PART NUMBER F530S 9246 9B 1M
A
DATE CODE (YYWW) YY = YEAR WW = WEEK
IRL3402S
Tape & Reel Information
D2Pak
TRR
1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153)
1.60 (.063) 1.50 (.059) 0.368 (.0145) 0.342 (.0135)
FEED DIRECTION 1.85 (.073)
1.65 (.065)
11.60 (.457) 11.40 (.449)
15.42 (.609) 15.22 (.601)
24.30 (.957) 23.90 (.941)
TRL
10.90 (.429) 10.70 (.421) 1.75 (.069) 1.25 (.049) 16.10 (.634) 15.90 (.626) 4.72 (.136) 4.52 (.178)
FEED DIRECTION
13.50 (.532) 12.80 (.504)
27.40 (1.079) 23.90 (.941)
4
330.00 (14.173) MAX.
60.00 (2.362) MIN.
NOTES : 1. COMFORMS TO EIA-418. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION MEASURED @ HUB. 4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039) 24.40 (.961) 3
30.40 (1.197) MAX. 4
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 03/04

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